Integrated circuits are made up of millions of active devices formed in or on a substrate, such as a silicon wafer. The active devices are chemically and physically connected onto a substrate and are interconnected through the use of multilevel interconnects to form functional circuits. Typical multilevel interconnects comprise a first metal layer, an interlevel dielectric layer, and sometimes a third and subsequent metal layers. Interlevel dielectrics, such as doped and undoped silicon dioxide (SiO2) and/or low-κ dielectrics, are used to electrically isolate the different metal layers.
The electrical connections between different interconnection levels are made through the use of metal vias. U.S. Pat. No. 5,741,626, for example, describes a method for preparing dielectric TaN layers. Moreover, U.S. Pat. No. 4,789,648 describes a method for preparing multiple metallized layers and metallized vias in insulator films. In a similar manner, metal contacts are used to form electrical connections between interconnection levels and devices formed in a well. The metal vias and contacts may be filled with various metals and alloys, such as, for example, titanium (Ti), titanium nitride (TiN), aluminum copper (Al—Cu), aluminum silicon (Al—Si), copper (Cu), tungsten (W), and combinations thereof (hereinafter referred to as “via metals”).
The via metals generally employ an adhesion layer (i.e., a barrier film), such as a titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN) barrier film, to adhere the via metals to the SiO2 substrate. At the contact level, the barrier film acts as a diffusion barrier to prevent the via metals from reacting with SiO2.
In one semiconductor manufacturing process, metal vias and/or contacts are formed by a blanket metal deposition followed by a chemical-mechanical polishing (CMP) step. In a typical process, via holes are etched through an interlevel dielectric (ILD) to interconnection lines or to a semiconductor substrate. Next, a barrier film is formed over the ILD and is directed into the etched via hole. Then, a via metal is blanket-deposited over the barrier film and into the via hole. Deposition is continued until the via hole is filled with the blanket-deposited metal. Finally, the excess metal is removed by chemical-mechanical polishing (CMP) to form metal vias. Processes for manufacturing and/or CMP of vias are disclosed in U.S. Pat. Nos. 4,671,851, 4,910,155, and 4,944,836.
CMP combines a chemical treatment of a substrate with a mechanical removal of the chemically treated layer. Typical CMP systems contain a chemical-mechanical polishing composition which is applied to a substrate between the substrate and a polishing pad that is moved relative to the substrate to effect the polishing of the substrate. CMP is becoming a more important process in the manufacture of semiconductor surfaces because more active devices are being packed into smaller areas in substrates and because unconventional metals, such as copper, are being used in order to improve the over-all performance of the circuits. More active devices in a given area on a semiconductor substrate require better planarization techniques due to the unevenness of the topography formed by the active devices themselves or of the topography of the layers formed over the active devices. Because many layers of metals and ILDs are formed successively one on top of another, each layer needs to be planarized to a high degree if higher resolution lithographic processes are to be used to form smaller and a higher number of active devices on a layer in a substrate.
The mechanical kinetics of CMP for a blanket deposited metal into vias in an ILD is explained by the Preston equation given by:(ΔH/Δt)=Kp(L/A)(Δs/Δt),where ΔH/Δt is the removal rate of the material in terms of change in height per unit time of polishing, L is the load imposed over a surface area A, Δs/Δt is the relative velocity of the pad to the substrate, and Kp is Preston's coefficient. The equation predicts that, for a given (L/A), the weight loss of the polished material is proportional to the amount of travel, and it remains invariant with time. The polishing rate increases with the pressure (L/A) and velocity. In other words, the removal rate is a linear function of pressure, so that high points are polished more rapidly, and the surface quickly becomes planar.
A CMP system ideally results in a polished planar surface without residual metal films on the polished surface of the ILD, and with all of the vias having metal at heights that are even with the level of the polished surface of the ILD. However, once the high points are quickly polished, the load is shared by lower points which are now within reach of the pad, thereby resulting in a relatively lower polishing pressure. After total removal of the metal layer from the surface of the ILD, the polishing is shared between the metal layer that is level with the ILD surface and the ILD itself. Since the polishing rate of the metal is different from that of the ILD, and, in the case of copper, greater than that of the ILD, metal is removed from further below the level of the ILD, thus leaving spaces. The formation of these spaces is known in the art as dishing.
Severe dishing in large metal active devices is a source of yield loss, especially when it occurs at lower levels of the substrate, where dishing causes trapped metal defects in the above lying layer(s). Furthermore, the longer time needed to remove the thicker metal overburden on the narrowest metal vias is one of the main culprits responsible for the low throughput and yield loss in the CMP process.
Typical metal CMP compositions contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium. U.S. Pat. No. 5,244,534, for example, discloses a chemical-mechanical polishing composition containing alumina, hydrogen peroxide, and either potassium or ammonium hydroxide, which is useful in removing tungsten with little removal of the underlying insulating layer. U.S. Pat. No. 5,209,816 discloses a chemical-mechanical polishing composition useful for polishing aluminum that comprises perchloric acid, hydrogen peroxide, and a solid abrasive material in an aqueous medium. U.S. Pat. No. 5,340,370 discloses a tungsten polishing composition comprising potassium ferricyanide, potassium acetate, acetic acid, and silica. U.S. Pat. No. 5,391,258 and U.S. Pat. No. 5,476,606 disclose chemical-mechanical polishing compositions for polishing a composite of metal and silica which includes an aqueous medium, abrasive particles, and an anion which controls the rate of silica removal. U.S. Pat. No. 5,770,095 discloses polishing compositions comprising an oxidizing agent, a chemical agent, and an etching agent selected from aminoacetic acid and amidosulfuric acid. Other polishing compositions for use in CMP applications are described in U.S. Pat. Nos. 4,956,313, 5,137,544, 5,157,876, 5,354,490, and 5,527,423.
Barrier films of titanium, titanium nitride, and like metals, such as tungsten, are chemically active in general. Thus, such barrier films are similar in chemical nature to via metals. As a result, a single polishing composition can be used effectively to polish both Ti/TiN barrier films and via metals at similar rates. Ta and TaN barrier films, however, are significantly different from Ti, TiN, and like barrier films. Ta and TaN are relatively inert in chemical nature as compared to Ti and TiN. Accordingly, the aforementioned polishing compositions are significantly less effective at polishing tantalum layers than they are at polishing titanium layers (e.g., the tantalum removal rate is significantly lower than the titanium removal rate). While via metals and barrier metals are conventionally polished with a single composition due to their similarly high removal rates, joint polishing of via metals and tantalum and similar materials using conventional polishing compositions can result in undesirable effects, such as oxide erosion and via metal dishing.
In many CMP operations, silicon dioxide is utilized as the underlying dielectric material. Examples of such operations are: Shallow Trench Isolation (STI), Cu/Ta damascene metal polish, and tungsten plug formation. For all of these CMP operations, erosion of the underlying dielectric material can lead to an excessive localized removal of the material being polished (e.g., nitride for STI, Cu for Cu/Ta polishing, and tungsten for tungsten plugs). In addition, changes in the thickness of the dielectric material can result in an unpredictable electrical performance and can also reduce planarity of the polished layers and/or subsequently deposited layers. As dimensions decrease and wafer sizes increase, these undesirable effects can limit yields. Therefore, there is a need for a composition and method of reducing dielectric material polish rates in an economical fashion. A composition that demonstrates self-stopping behavior on the dielectric layer is particularly desirable.
The invention provides such a composition and method. These and other characteristics and advantages of the invention will be apparent from the description of the invention provided herein.